The downscaling of semiconductor devices such as complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) into the sub-micron domain and beyond, e.g. into the sub-100 nm domain, is not without problems. One of these problems is that the shrinking dimensions of the MOSFETs are accompanied by an increase in undesirable device characteristics such as short channel effects, poor current drive and leakage currents, which limit the application domains in which such devices can be used. For instance, the high leakage current prohibits use of such small transistors in low power applications, unless additional measures are included in the transistor design to reduce these undesirable effects, which add to the complexity and cost of the IC manufacturing process.
For this reason, other device architectures have been investigated to determine if these architectures are better equipped to handle device requirements in the sub-micron domain. Such architectures include multi-gate devices, gate-all-around nanowires and tunnel and impact ionization transistors. Especially tunnel transistors appear to be promising candidates for such application domains because they do not suffer from short-channel effects and have an extremely low off-state current. Moreover, due to the fact that the main carrier transport in their off-state comprises a tunneling mechanism through a potential barrier rather than thermionic emission over a potential barrier, a very steep transition from their off-state to their on-state may be achieved. Sub-threshold slope values of less than 10 mV/decade have already been reported, which is a considerable improvement over the optimum value that can be achieved with bulk transistors, which is approximately 60 mV/decade. In addition, due to the fact that the on-current of a tunnel transistor is only weakly dependent of the gate length, tunnel transistors are far less sensitive to variations in the lithography than MOSFETs. An example of a tunnel FET is disclosed in EP 1 901 354 A1.
One of the drawbacks of tunnel transistors such as tunnel FETs is that their current drive capability is less than that of conventional transistors such as MOSFETs. However, it has been recently demonstrated that the use of semiconductor materials other than silicon, e.g. germanium (Ge) or silicon-germanium (SiGe), can significantly improve performance of a tunnel transistor because the thickness of the tunnel barrier is significantly reduced when using such lower bandgap materials. This makes such tunnel transistors interesting candidates for low power application domains because good drive currents can be achieved in combination with low leakage currents in the off state of the device.
Another example of a known tunnel FET is shown in FIG. 1. A substrate 10 comprises a source region 14 that is heavily doped with a p-type impurity (i.e. a p+ region) and a drain region 16 that is heavily doped with an n-type impurity (i.e. a n+ region). A lightly doped p-type channel region 12 ((i.e. a p− region) is located between regions 12 and 14, and is separated from a gate electrode 20 by a gate dielectric layer 18. Such a tunnel FET is also known as a p-i-n device due to the insulating nature of the p− channel region 12. In operation, a tunnel barrier is formed at the source region 14 when a positive voltage is applied to the gate electrode 20, thus forming an inversion layer extending the n+ drain region 16 deep into the p+ source region 14. This inversion layer creates a potential energy barrier that can be tunneled by the electrons in the channel region 12.
A drawback of such tunnel transistors is that the asymmetric implant required to define the p-i-n structure of the tunnel transistor makes it difficult to achieve very small gate lengths due to limitations in the alignment accuracy during the masking and lithographic processes. This negatively affects the integration density for such devices. In addition, the manufacturing of such tunnel transistors generally requires more process steps compared to the manufacturing of conventional transistors, such that tunnel transistors are typically more costly to manufacture.